Ferroelectric field effect transistors (FeFETs) have been envisioned and are still being researched as ultra-low power non-volatile memory devices. The most prominent non-volatile transistor architecture to date is, however, still represented by FLASH devices which are subgroups of charge storage (CS) based transistors. In this regard, CS-based transistors and FLASH devices may be considered to be the same “type” of devices. When compared to these FLASH devices, FeFETs require only a fraction of the write voltages and can be switched in the nanosecond regime. The write operation can either mean to program a memory cell into the binary “0” or “off” state, or programming (erasing) the memory cell to a binary “1” or “on” state, respectively. The difference in write voltages between FeFETs and charge storage based transistors (FLASH devices) originates from the fundamentally different underlying physical mechanisms used for storing binary data.
In order to represent binary states, FLASH devices use the injection of charge carriers (e.g., electrons) into a charge storing layer (e.g., a floating gate or trap layer) which thereby shifts the threshold voltage of the storing transistor. Since the charge carrier injection mechanism (e.g., hot carrier injection (HCl) or Fowler-Nordheim Tunneling (FN)) is only efficient to a certain degree (i.e., only a small fraction of all available electrons reach the probability to tunnel into the charge storing layer), the write speed of these devices is limited to the microsecond and millisecond regime for HCl and FN, respectively. Furthermore, in order to provide proper data retention, the tunnel oxide cannot be scaled down arbitrarily (i.e., made thinner), which in turn results in the elevated operational voltages of these devices.
FeFETs, however, are solely written by the electric field which develops when a potential difference exists between the gate and the source/drain/bulk regions of a transistor. Accordingly, FeFETs do not rely on charge storage for the representation of binary states. Due to the electric field across the ferroelectric material present in FeFETs, atoms are shifted into one of two stable positions or polarization states (dipoles). If such a ferroelectric material is incorporated into the transistor gate stack, the permanent dipole accompanying the displacement of atoms alters the threshold voltage of a transistor. The magnitude of the electric field, as well as the duration during which the electric field is applied, are both lower for FeFETs than for CS based transistors. For example, the electric field (E-field) for FeFETs can vary from ˜0.1 kilovolts/centimeter (kV/cm) to ˜1 megavolt/cm (MV/cm), while the E-field for CS-based transistors is on the order of ˜10 MV/cm. Similarly, the duration for write operations for a FeFET can vary from 100 picosecond (ps) to 100 nanoseconds (ns), while the write duration for CS-based transistors is on the order of 1 microsecond (μs) to 1 millisecond (ms).
Although the underlying physical mechanisms of CS-based and ferroelectric transistors are quite different, the memory architectures concerning one-transistor (1T) approaches are similar. Just as in CS-based transistors, NAND, NOR and AND architectures have been proposed for FeFETs. Accordingly, FeFETs are affected by “disturb” issues known to exist for FLASH memories. Cells not selected for programming are subjected to electric field effects simply by sharing the same signal line (e.g., wordlines and bitlines) thereby introducing uncertainty with respect to the binary state of a given memory cell. Secondly, by writing cells, the electric field of cells being addressed can “bleed” over to the adjacent cells.
For example, in charge storage based transistors, cells adjacent to the cells being programmed can suffer from unwanted charge storage. Similarly, in ferroelectric transistors, those cells neighboring the cells to be programmed can suffer from or be “disturbed” by a polarization change. For both CS-based and ferroelectric transistors, the disturb effect originates from the fact that non-selected cells are exposed to unwanted electrical fields occurring when a selected cell is programmed. With regard to both FeFETs and CS-based transistors, there are approaches to avoid the “disturbance” of binary states. In FLASH-based devices, inhibit schemes may be employed (e.g., global or local self-boost program inhibit schemes for NAND FLASH) to reduce any disturb issues. FeFET arrays may use the VDD/2 or VDD/3 scheme that provides known advantages, or adapt inhibit schemes known to be effective for CS-based transistors.